AT91SAM9G20B-CFU【PDF 12/42 页】IC MCU ARM9 247-LFBGA

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6384DS–ATARM–13-Jan-10

AT91SAM9G20 Summary

Periodic Interval Timer (PIT)

– 20-bit Interval Timer plus 12-bit Interval Counter

Watchdog Timer (WDT)

– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock

Real-time Timer (RTT)

– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler

One 4-channel 10-bit Analog-to-Digital Converter

Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC)

– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os

– Input Change Interrupt Capability on Each I/O Line

– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output

– All I/O Lines are Schmitt Trigger Inputs

Peripheral DMA Controller Channels (PDC)

One Two-slot MultiMedia Card Interface (MCI)

– SDCard/SDIO and MultiMediaCard Compliant

– Automatic Protocol Control and Fast Automatic Data Transfers with PDC

One Synchronous Serial Controller (SSC)

– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter

– IS Analog Interface Support, Time Division Multiplex Support

– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)

– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation, Manchester Encoding/Decoding

– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support

– Full Modem Signal Control on USART0

Two 2-wire UARTs

Two Master/Slave Serial Peripheral Interfaces (SPI)

– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects

– Synchronous Communications

Two Three-channel 16-bit Timer/Counters (TC)

– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel

– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability

– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2

One Two-wire Interface (TWI)

– Compatible with Standard Two-wire Serial Memories

– One, Two or Three Bytes for Slave Address

– Sequential Read/Write Operations

– Master, Multi-master and Slave Mode Operation

– Bit Rate: Up to 400 Kbits

– General Call Supported in Slave Mode

– Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode

IEEE 1149.1 JTAG Boundary Scan on All Digital Pins

Required Power Supplies

– 0.9V to 1.1V for VDDBU, VDDCORE, VDDPLL

– 1.65 to 3.6V for VDDOSC

– 1.65V to 3.6V for VDDIOP (Peripheral I/Os)

– 3.0V to 3.6V for VDDUSB

– 3.0V to 3.6V VDDANA (Analog-to-digital Converter)

– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)

Available in a 217-ball LFBGA and 247-ball TFBGA RoHS-compliant Package

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